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By John G. Webster (Editor)

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Furthermore, to reduce power as much as possible, the predecoder and decoder gates should have a near-minimum current. Even though typical n–p–n transistors have current gains, ͱ, of around 100, the overall emitter-follower current gain over the current in the ECL current-steering gate is considerably less. Consider a 4 : 1 emitter-follower-current to gate-current ratio and a 550 mV voltage swing; the high static noise margin is already reduced by 24 mV from the emitter-follower in this configuration for a ͱ of 100.

20. 944% in the case of the 66-bit adder as shown in Table 2. CONCLUSIONS This article presented mixed CMOS/BiCMOS parallel adders, which is an improvement over the high-speed area-time optimal adders that have been realized by CMOS static circuits. The CMOS parallel adders suffer from the speed penalty as a result of long wire interconnects and large fanout sites. In order to achieve higher speed in the carry computation, highspeed technology is needed. BiCMOS technology suitable for high-speed circuits is chosen for the implementation of the basic cells in the carry-generation circuit to drive large-fanout and capacitive loads.

These n–p–n variations increase current drive (ͱ) at a cost of 2 Vbe voltage drops and greater overshoot tendencies. 300 BiCMOS MEMORY CIRCUITS turn-on transient die off. Therefore, the n–p–n current gain increases, returning to its nominal value, which injects more current into the output node and causes the circuit to overshoot. Consider how the f T doubler compares to other Darlington configurations for stability. The effective current gain of the f T doubler is βeff = β × AD2 + AQ2 AD2 + AQ2 /β ≈β× 1+ AQ2 (2) AD2 where AQ2 and AD2 are the emitter areas of n–p–n Q2 and diode D2, respectively.

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