By Andreas Kerber, Eduard Cartier (auth.), Tibor Grasser (eds.)
This e-book presents a single-source connection with one of many tougher reliability concerns plaguing sleek semiconductor applied sciences, unfavourable bias temperature instability. Readers will make the most of state-of-the artwork assurance of analysis in issues reminiscent of time established illness spectroscopy, anomalous illness habit, stochastic modeling with extra metastable states, multiphonon idea, compact modeling with RC ladders and implications on machine reliability and lifetime.
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Extra resources for Bias Temperature Instability for Devices and Circuits
Kaczer, T. Grasser, Ph. J. Roussel, J. Martin-Martinez2, R. O’Connor, B. J. O’Sullivan, G. Groeseneken, “Ubiquitous Relaxation in BTI stressing – New Evaluation and Insights”, inProc. IRPS, pp. 20–27, 2008. 22. A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, G. E. Maes, U. Schwalke, “Charge trapping in SiO2/HfO2 gate dielectrics: Comparison between charge-pumping and pulsed ID –VG ”, Microelectronic Engineering, Vol. 72, pp. 267–272, 2004. 23. E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C.
Our approach to harmonize all conditions and to get rid of the above-described technical difficulties is to make use of the poly-heater technique, cf. Fig. 7a. During stress a certain stress bias (VGS ) is applied to the gate and the (previously calibrated) heater generates an elevated device temperature (TS ) for a defined stress time tS . Before initiating the recovery/characterization cycle, the heater is switched off, the device reaching ambient (chuck) temperature within a couple of seconds (tD ).
Chudzik, B. Doris, R. Mo, J. Sleight, E. Cartier, C. Dewan, D. Park, H. Bu, W. Natzle, W. Yan, C. Ouyang, K. Henson, D. Boyd, S. Callegari, R. Carter, D. Casarotto, M. Gribelyuk, M. Hargrove, W. He, Y. Kim, B. Linder, N. Moumen, V. K. Paruchuri, J. Stathis, M. Steen, A. Vayshenker, X. Wang, S. Zafar, T. Ando, R. Iijima, M. Takayanagi, V. Narayanan, R. Wise, Y. Zhang, R. Divakaruni, M. Khare, and T. C. Chen, “High-performance high-k/metal gates for 45 nm CMOS and beyond with gate-first processing,” in Symp.