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By Lam, Tak-Kei

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Nagoya. A new method to express functional permissibilities for LUT based FPGAS and its applications. In ICCAD ’96: Proceedings of the 1996 IEEE/ACM international conference Concept of Logic Rewiring 35 on Computer-aided design, pages 254–261, Washington, DC, USA, 1996. IEEE Computer Society. ISBN: 0-8186-7597-7. X. -K. -L. Wu. ECR: A low complexity generalized error cancellation rewiring scheme. In DAC ’10: Proceedings of the 47th Design Automation Conference, pages 511–516, New York, 2010. ACM.

In Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, pages 373–377, February 1993. 386447. F. S. Chim, T. K. -L. Wu. On improved scheme for digital circuit rewiring and application on further improving FPGA technology mapping. In Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific, pages 197–202, 2009. 4796480. -S. -K. -L. Wu, and H. Fan. On structural analysis and efficiency for graph-based rewiring techniques. IEICE Transactions, E94(12):2853–2865, 2011.

The authors of Tang et al. (2003) carried out a quantitative analysis on the rewiring ability of these RAR-based rewiring techniques. 2 Node-Based Network Addition and Removal (NAR) So far, we have discussed the most basic but the most important rewiring concepts and various rewiring techniques. In this section, another kind of logic restructuring technique will be introduced. This kind of techniques is conceptually different from the rewiring concepts discussed previously in such a way that it is node-based instead of wire-based.

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